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MT9045 T1/E1/OC3 System Synchronizer
Data Sheet Features
* Supports AT&T TR62411 and Bellcore GR-1244CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Supports ITU-T G.813 Option 1 clocks for 2048 kbit/s interfaces Supports ITU-T G.812 Type IV clocks for 1,544 kbit/s interfaces and 2,048 kbit/s interfaces Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interfaces Selectable 19.44 MHz, 1.544MHz, 2.048MHz or 8kHz input reference signals Provides C1.5, C2, C4, C6, C8, C16, and C19 (STS-3/OC3 clock divided by 8) output clock signals Provides 5 styles of 8 KHz framing pulses Holdover frequency accuracy of 0.05 PPM Holdover indication Attenuates wander from 1.9Hz Fast lock mode * * * * Ordering Information MT9045AN 48 pin SSOP -40C to +85C Provides Time Interval Error (TIE) correction Accepts reference inputs from two independent sources JTAG Boundary Scan
November 2003
* * * * *
Applications
* Synchronization and timing control for multitrunk T1,E1 and STS-3/OC3 systems ST-BUS clock and frame pulse sources
* * * * *
OSCi
OSCo
TCLR
LOCK
VDD
VSS
Master Clock TCK TDI TMS TRST TDO PRI SEC Prioor Secoor IEEE 1149.1a TIE Corrector Circuit
Virtual Reference DPLL Output Interface Circuit
Reference Select MUX Reference Monitor
Selected Reference TIE Corrector Enable Reference Select
State Select Input Impairment Monitor
State Select
C19o C1.5o C2o C4o C6o C8o C16o F0o F8o F16o RSP TSP
RSEL
Control State Machine Feedback
Frequency Select MUX
MS1 MS2
RST HOLDOVER PCCi FLOCK
FS1
FS2
Figure 1 - Functional Block Diagram Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912, France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08 1
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
MT9045
Description
Data Sheet
The MT9045 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/OC3 links. The MT9045 generates ST-BUS clock and framing signals that are phase locked to either a 19.44 MHz, 2.048MHz, 1.544MHz, or 8kHz input reference. The MT9045 is compliant with AT&T TR62411 and Bellcore GR-1244-CORE Stratum 3, Stratum 4 Enhanced, and Stratum 4 and ETSI ETS 300 011; and ITU-T G.813 Option 1 for 2048 kbit/s interfaces. It will meet the jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture range, phase change slope, holdover frequency and MTIE requirements for these specifications.
VSS RST TCLR SECOOR SEC PRI Vdd OSCo OSCi Vss F16o F0o RSP TSP F8o C1.5o Vdd LOCK C2o C4o C19o FLOCK Vss IC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SSOP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
TMS TCK TRST TDI TDO PRIOOR IC FS1 FS2 IC RSEL MS1 MS2 Vdd IC IC NC Vss PCCi HOLDOVER Vdd C6o C16o C8o
Figure 2 - Pin Connections
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Pin Description
Pin # 1,10, 23,31 2 Name VSS RST Ground. 0 Volts. (Vss pads). Description
Data Sheet
Reset (Input). A logic low at this input resets the MT9045. To ensure proper operation, the device must be reset after reference signal frequency changes and power-up. The RST pin should be held low to a minimum of 300ns. While the RST pin is low, all frame pulses except RST and TSP and all clock outputs except C6o, C16o and C19o are at logic high. The RST, TSP, C6o, C16o are at logic low during reset. The C19o is free-running during reset. Following a reset, the input reference source and output clocks and frame pulses are phase aligned as shown in Figure 13. TIE Circuit Reset (Input). A logic low at this input resets the Time Interval Error (TIE) correction circuit resulting in a realignment of input phase with output phase as shown in Figure 13. The TCLR pin should be held low for a minimum of 300ns. This pin is internally pulled down to VSS.
3
TCLR
4 5
SECOOR Secondary Reference Out Of Capture Range (Output). A logic high at this pin indicates that the secondary reference is off the nominal frequency by more than 17 ppm. SEC Secondary Reference (Input). This is one of two (PRI & SEC) input reference sources (falling edge) used for synchronization. One of four possible frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be used. The selection of the input reference is based upon the MS1, MS2, RSEL, and PCCi control inputs.This pin is internally pulled up to VDD. Primary Reference (Input). See pin description for SEC. This pin is internally pulled up to VDD. Positive Supply Voltage. +3.3VDC nominal. Oscillator Master Clock (CMOS Output). For crystal operation, a 20MHz crystal is connected from this pin to OSCi, see Figure 9. Not suitable for driving other devices. For clock oscillator operation, this pin is left unconnected, see Figure 8. Oscillator Master Clock (CMOS Input). For crystal operation, a 20MHz crystal is connected from this pin to OSCo, see Figure 9. For clock oscillator operation, this pin is connected to a clock source, see Figure 8. Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output). This is an 8kHz 61ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS operation at 8.192 Mb/s. See Figure 14. Frame Pulse ST-BUS 2.048Mb/s (CMOS Output). This is an 8kHz 244ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS operation at 2.048Mb/s and 4.096Mb/s. See Figure 14. Receive Sync Pulse (CMOS Output). This is an 8kHz 488ns active high framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for connection to the Siemens MUNICH-32 device. See Figure 15. Transmit Sync Pulse (CMOS Output). This is an 8kHz 488ns active high framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for connection to the Siemens MUNICH-32 device. See Figure 15. Frame Pulse (CMOS Output). This is an 8kHz 122ns active high framing pulse, which marks the beginning of a frame. See Figure 14.
6 7,17 28,35 8
PRI VDD OSCo
9
OSCi
11
F16o
12
F0o
13
RSP
14
TSP
15
F8o
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Pin Description (continued)
Pin # 16 18 19 20 21 22 24 25 26 27 29 30 Name C1.5o LOCK C2o C4o C19o FLOCK IC C8o C16o C6o HOLD OVER PCCi Description Clock 1.544MHz (CMOS Output). This output is used in T1 applications.
Data Sheet
Lock Indicator (CMOS Output). This output goes high when the PLL is frequency locked to the input reference. Clock 2.048MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s. Clock 4.096MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s and 4.096Mb/s. Clock 19.44MHz (CMOS Output). This output is used in OC3/STS3 applications. Fast Lock Mode (Input). Set high to allow the PLL to quickly lock to the input reference (less than 500 ms locking time). Internal Connection. Tie low for normal operation. Clock 8.192MHz (CMOS Output). This output is used for ST-BUS operation at 8.192Mb/s. Clock 16.384MHz (CMOS Output). This output is used for ST-BUS operation with a 16.384MHz clock. Clock 6.312 Mhz (CMOS Output). This output is used for DS2 applications. Holdover (CMOS Output). This output goes to a logic high whenever the PLL goes into holdover mode. Phase Continuity Control Input (Input). The signal at this pin affects the state changes between Primary Holdover Mode and Primary Normal Mode, and Primary Holdover Mode and Secondary Normal Mode. The logic level at this input is gated in by the rising edge of F8o. See Table 4. No connection. Leave open circuit Internal Connection. Tie low for normal operation. Mode/Control Select 2 (Input). This input determines the state (Normal, Holdover or Freerun) of operation. The logic level at this input is gated in by the rising edge of F8o. See Table 3. Mode/Control Select 1 (Input). The logic level at this input is gated in by the rising edge of F8o. See pin description for MS2. This pin is internally pulled down to VSS. Reference Source Select (Input). A logic low selects the PRI (primary) reference source as the input reference signal and a logic high selects the SEC (secondary) input. The logic level at this input is gated in by the rising edge of F8o. See Table 2. This pin is internally pulled down to VSS. Internal Connection. Tie low for normal operation. Frequency Select 2 (Input). This input, in conjunction with FS1, selects which of four possible frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be input to the PRI and SEC inputs. See Table 1. Frequency Select 1 (Input). See pin description for FS2. Internal Connection. Tie low for normal operation.
32 33,34 36
NC IC MS2
37 38
MS1 RSEL
39 40
IC FS2
41 42 43
FS1 IC
PRIOOR Primary Reference Out Of Capture Range (Output). A logic high at this pin indicates that the Primary reference is off the nominal frequency by more than 17 ppm.
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Pin Description (continued)
Pin # 44 45 46 47 48 Name TDO TDI TRST TCK TMS Description
Data Sheet
Test Serial Data Out (CMOS Output). JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG scan is not enable. Test Serial Data In (Input). JTAG serial test instructions and data are shifted in on this pin. This pin is internally pulled up to VDD. Test Reset (Input). Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. If not used, this pin should be held low. Test Clock (Input): Provides the clock to the JTAG test logic. This pin is internally pulled up to VDD. Test Mode Select (Input). JTAG signal that controls the state transitions of the TAP controller. This pin is internally pulled up to VDD.
Functional Description
The MT9045 is a Multitrunk System Synchronizer, providing timing (clock) and synchronization (frame) signals to interface circuits for T1 and E1 Primary Rate Digital Transmission links. Figure 1 is a functional block diagram which is described in the following sections. Reference Select MUX Circuit The MT9045 accepts two simultaneous reference input signals and operates on their falling edges. Either the primary reference (PRI) signal or the secondary reference (SEC) signal can be selected as input to the TIE Corrector Circuit. The selection is based on the Control, Mode and Reference Selection of the device. See Table 1 and Table 4. Frequency Select MUX Circuit The MT9045 operates with one of four possible input reference frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz). The frequency select inputs (FS1 and FS2) determine which of the four frequencies may be used at the reference inputs (PRI and SEC). Both inputs must have the same frequency applied to them. A reset (RST) must be performed after every frequency select input change. See Table 1.
FS2 0 0 1 1
FS1 0 1 0 1
Input Frequency 19.44MHz 8kHz 1.544MHz 2.048MHz
Table 1 - Input Frequency Selection Time Interval Error (TIE) Corrector Circuit The TIE corrector circuit, when enabled, prevents a step change in phase on the input reference signals (PRI or SEC) from causing a step change in phase at the input of the DPLL block of Figure 1. During reference input rearrangement, such as during a switch from the primary reference (PRI) to the secondary reference (SEC), a step change in phase on the input signals will occur. A phase step at the input of the DPLL would lead to unacceptable phase changes in the output signal.
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TCLR Resets Delay Control Circuit Control Signal
Data Sheet
Delay Value
PRI or SEC from Reference Select Mux
Programmable Delay Circuit
Virtual Reference to DPLL Compare Circuit
TIE Corrector Enable from State Machine
Feedback Signal from Frequency Select MUX
Figure 3 - TIE Correction Circuit As shown in Figure 3, the TIE Corrector Circuit receives one of the two reference (PRI or SEC) signals, passes the signal through a programmable delay line, and uses this delayed signal as an internal virtual reference, which is input to the DPLL. Therefore, the virtual reference is a delayed version of the selected reference. During a switch from one reference to the other, the State Machine first changes the mode of the device from Normal to Holdover. In Holdover Mode, the DPLL no longer uses the virtual reference signal, but generates an accurate clock signal using storage techniques. The Compare Circuit then measures the phase delay between the current phase (feedback signal) and the phase of the new reference signal. This delay value is passed to the Programmable Delay Circuit (See Figure 3). The new virtual reference signal is now at the same phase position as the previous reference signal would have been if the reference switch not taken place. The State Machine then returns the device to Normal Mode. The DPLL now uses the new virtual reference signal, and since no phase step took place at the input of the DPLL, no phase step occurs at the output of the DPLL. In other words, reference switching will not create a phase change at the input of the DPLL, or at the output of the DPLL. Since internal delay circuitry maintains the alignment between the old virtual reference and the new virtual reference, a phase error may exist between the selected input reference signal and the output signal of the DPLL. This phase error is a function of the difference in phase between the two input reference signals during reference rearrangements. Each time a reference switch is made, the delay between input signal and output signal will change. The value of this delay is the accumulation of the error measured during each reference switch. The programmable delay circuit can be zeroed by applying a logic low pulse to the TIE Circuit Reset (TCLR) pin. A minimum reset pulse width is 300ns. This results in a phase alignment between the input reference signal and the output signal as shown in Figure 14. The speed of the phase alignment correction is limited to 5ns per 125us, and convergence is in the direction of least phase travel. The state diagram of Figure 7 indicates which state changes the TIE Corrector Circuit is activated.
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Digital Phase Lock Loop (DPLL)
Data Sheet
As shown in Figure 4, the DPLL of the MT9045 consists of a Phase Detector, Limiter, Loop Filter, Digitally Controlled Oscillator, and a Control Circuit.
Virtual Reference from TIE Corrector
Phase Detector
Limiter
Loop Filter
Digitally Controlled Oscillator
DPLL Reference to Output Interface Circuit
Feedback Signal from Frequency Select MUX
State Select from Input Impairment Monitor
Control Circuit
State Select from State Machine
Figure 4 - DPLL Block Diagram Phase Detector - the Phase Detector compares the virtual reference signal from the TIE Corrector circuit with the feedback signal from the Frequency Select MUX circuit, and provides an error signal corresponding to the phase difference between the two. This error signal is passed to the Limiter circuit. The Frequency Select MUX allows the proper feedback signal to be externally selected (e.g., 8kHz, 1.544MHz, 2.048MHz or 19.44MHz). Limiter - the Limiter receives the error signal from the Phase Detector and ensures that the DPLL responds to all input transient conditions with a maximum output phase slope of 5ns per 125us. This is well within the maximum phase slope of 7.6ns per 125us or 81ns per 1.326ms specified by AT&T TR62411 and Bellcore GR-1244-CORE, respectively. Loop Filter - the Loop Filter is similar to a first order low pass filter with a 1.9 Hz cutoff frequency for all four reference frequency selections (8kHz, 1.544MHz, 2.048MHz or 19.44MHz). This filter ensures that the jitter transfer requirements in ETS 300 011 and AT&T TR62411 are met. Control Circuit - the Control Circuit uses status and control information from the State Machine and the Input Impairment Circuit to set the mode of the DPLL. The three possible modes are Normal, Holdover and Freerun. Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the Loop Filter, and based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is dependent on the state of the MT9045. In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input reference signal. In Holdover Mode, the DCO is free running at a frequency equal to the last (less 30ms to 60ms) frequency the DCO was generating while in Normal Mode. In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20MHz source. Lock Indicator - If the PLL is in frequency lock (frequency lock means the center frequency of the PLL is identical to the line frequency), and the input phase offset is small enough such that no phase slope limiting is exhibited, then the lock signal will be set high. For specific Lock Indicator design recommendations see the Applications - Lock Indicator section.
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Output Interface Circuit
Data Sheet
The output of the DCO (DPLL) is used by the Output Interface Circuit to provide the output signals shown in Figure 5. The Output Interface Circuit uses four Tapped Delay Lines followed by a T1 Divider Circuit, an E1 Divider Circuit, and a DS2 Divider Circuit to generate the required output signals. Four tapped delay lines are used to generate 16.384MHz, 12.352MHz, 12.624MHz and 19.44 MHz signals. The E1 Divider Circuit uses the 16.384MHz signal to generate four clock outputs and three frame pulse outputs. The C8o, C4o and C2o clocks are generated by simply dividing the C16o clock by two, four and eight respectively. These outputs have a nominal 50% duty cycle. The T1 Divider Circuit uses the 12.384MHz signal to generate the C1.5o clock by dividing the internal C12 clock by eight. This output has a nominal 50% duty cycle. The DS2 Divider Circuit uses the 12.624 MHz signal to generate the clock output C6o. This output has a nominal 50% duty cycle.
T1 Divider 12MHz Tapped Delay Line C1.5o
E1 Divider From DPLL Tapped Delay Line 16MHz
C2o C4o C8o C16o F0o F8o F16o
Tapped Delay Line
12MHz
DS2 Divider
C6o
Tapped Delay Line
19MHz
C19o
Figure 5 - Output Interface Circuit Block Diagram
The frame pulse outputs (F0o, F8o, F16o, TSP, and RSP) are generated directly from the C16 clock. The T1 and E1 signals are generated from a common DPLL signal. Consequently, all frame pulse and clock outputs are locked to one another for all operating states, and are also locked to the selected input reference in Normal Mode. See Figures 14 & 16. All frame pulse and clock outputs have limited driving capability, and should be buffered when driving high capacitance (e.g., 30pF) loads.
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Input Impairment Monitor
Data Sheet
This circuit monitors the input signal to the DPLL and automatically enables the Holdover Mode (Auto-Holdover) when the frequency of the incoming signal is outside the Auto-Holdover capture range. (See AC Electrical Characteristics - Performance). This includes a complete loss of incoming signal, or a large frequency shift in the incoming signal. When the incoming signal returns to normal, the DPLL is returned to Normal Mode with the output signal locked to the input signal. The holdover output signal in the MT9045 is based on the incoming signal 30ms minimum to 60ms prior to entering the Holdover Mode. The amount of phase drift while in holdover is negligible because the Holdover Mode is very accurate (e.g., 0.05ppm). Consequently, the phase delay between the input and output after switching back to Normal Mode is preserved. State Machine Control As shown in Figure 1, this state machine controls the Reference Select MUX, the TIE Corrector Circuit and the DPLL. Control is based on the logic levels at the control inputs RSEL, MS1, MS2 and PCCi (See Figure 6). When switching from Primary Holdover to Primary Normal, the TIE Corrector Circuit is enabled when PCCi = 1, and disabled when PCCi = 0. All state machine changes occur synchronously on the rising edge of F8o. See the Control and Mode of Operation section for full details.
To Reference Select MUX To TIE Corrector Enable To DPLL State Select
RSEL
Control State Machine
PCCi
MS1
MS2
Figure 6 - Control State Machine Block Diagram Master Clock The MT9045 can use either a clock or crystal as the master timing source. For recommended master timing circuits, see the Applications - Master Clock section.
Control and Mode of Operation
The active reference input (PRI or SEC) is selected by the RSEL pin as shown in Table 2.
RSEL 0 1
Input Reference PRI SEC
Table 2 - Input Reference Selection
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MS2 0 0 1 1 MS1 0 1 0 1 Mode NORMAL HOLDOVER FREERUN Reserved
Data Sheet
Table 3 - Operating Modes and States The MT9045 has three possible modes of operation, Normal, Holdover and Freerun. As shown in Table 3, Mode/Control Select pins MS2 and MS1 select the mode and method of control. Refer to Table 4 and Figure 7 for details of the state change sequences. Normal Mode Normal Mode is typically used when a slave clock source, synchronized to the network is required. In Normal Mode, the MT9045 provides timing (C1.5o, C2o, C4o, C8o, C16o and C19o) and frame synchronization (F0o, F8o, F16o, TSP and RSP) signals, which are synchronized to one of two reference inputs (PRI or SEC). The input reference signal may have a nominal frequency of 8kHz, 1.544MHz, 2.048MHz or 19.44MHz. From a reset condition, the MT9045 will take up to 30 seconds (see AC Electrical Characteristics) of input reference signal to output signals which are synchronized (phase locked) to the reference input. The selection of input references is control dependent as shown in state Table 4. The reference frequencies are selected by the frequency control pins FS2 and FS1 as shown in Table 1. Fast Lock Mode Fast Lock Mode is a submode of Normal Mode, it is used to allow the MT9045 to lock to a reference more quickly than Normal Mode will allow. Typically, the PLL will lock to the incoming reference within 500ms if the FLOCK pin is set high. Holdover Mode Holdover Mode is typically used for short durations (e.g., 2 seconds) while network synchronization is temporarily disrupted. In Holdover Mode, the MT9045 provides timing and synchronization signals, which are not locked to an external reference signal, but are based on storage techniques. The storage value is determined while the device is in Normal Mode and locked to an external reference signal. When in Normal Mode, and locked to the input reference signal, a numerical value corresponding to the MT9045 output reference frequency is stored alternately in two memory locations every 30ms. When the device is switched into Holdover Mode, the value in memory from between 30ms and 60ms is used to set the output frequency of the device. The frequency accuracy of Holdover Mode is 0.05ppm, which translates to a worst case 35 frame (125us) slips in 24 hours. This satisfies the AT&T TR62411 and Bellcore GR-1244-CORE Stratum 3 requirement of 0.37ppm (255 frame slips per 24 hours). Two factors affect the accuracy of Holdover Mode. One is drift on the Master Clock while in Holdover Mode, drift on the Master Clock directly affects the Holdover Mode accuracy. Note that the absolute Master Clock (OSCi) accuracy does not affect Holdover accuracy, only the change in OSCi accuracy while in Holdover. For example, a 32ppm master clock may have a temperature coefficient of 0.1ppm per degree C. So a 10 degree change in
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temperature, while the MT9045 is in Holdover Mode may result in an additional offset (over the frequency accuracy of 1ppm. Which is much greater than the 0.05ppm of the MT9045.
Data Sheet 0.05ppm) in
The other factor affecting accuracy is large jitter on the reference input prior (30ms to 60ms) to the mode switch. For instance, jitter of 7.5UI at 700Hz may reduce the Holdover Mode accuracy from 0.05ppm to 0.10ppm. Freerun Mode Freerun Mode is typically used when a master clock source is required, or immediately following system power-up before network synchronization is achieved. In Freerun Mode, the MT9045 provides timing and synchronization signals which are based on the master clock frequency (OSCi) only, and are not synchronized to the reference signals (PRI and SEC). The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a 32ppm output clock is required, the master clock must also be 32ppm. See Applications - Crystal and Clock Oscillator sections.
MT9045 Measures of Performance
The following are some synchronizer performance indicators and their corresponding definitions. Intrinsic Jitter Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output. It is measured by applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Intrinsic jitter may also be measured when the device is in a non-synchronizing mode, such as free running or holdover, by measuring the output jitter of the device. Intrinsic jitter is usually measured with various bandlimiting filters depending on the applicable standards. In the MT9045, the intrinsic Jitter is limited to less than 0.02UI on the 2.048MHz and 1.544MHz clocks. Jitter Tolerance Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied jitter magnitude and jitter frequency depends on the applicable standards. Jitter Transfer Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. For the MT9045, two internal elements determine the jitter attenuation. This includes the internal 1.9Hz low pass loop filter and the phase slope limiter. The phase slope limiter limits the output phase slope to 5ns/125us. Therefore, if the input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the maximum output phase slope will be limited (i.e., attenuated) to 5ns/125us.
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Data Sheet
The MT9045 has twelve outputs with three possible input frequencies (except for 19.44MHz, which is internally divided to 8KHz) for a total of 36 possible jitter transfer functions. Since all outputs are derived from the same signal, the jitter transfer values for the four cases, 8kHz to 8kHz, 1.544MHz to 1.544MHz and 2.048MHz to 2.048MHz can be applied to all outputs. It should be noted that 1UI at 1.544MHz is 644ns, which is not equal to 1UI at 2.048MHz, which is 488ns. Consequently, a transfer value using different input and output frequencies must be calculated in common units (e.g., seconds) as shown in the following example. What is the T1 and E1 output jitter when the T1 input jitter is 20UI (T1 UI Units) and the T1 to T1 jitter attenuation is 18dB? - A ----- 20
OutputT1 = InputT1 x10
- 18 ------- 20 OutputT1 = 20 x10 = 2.5UI ( T1 ) ( 1UIT1 ) OutputE1 = OutputT1 x --------------------( 1UIE1 ) ( 644ns ) OutputE1 = OutputT1 x ------------------- = 3.3UI ( T1 ) ( 488ns )
Using the above method, the jitter attenuation can be calculated for all combinations of inputs and outputs based on the three jitter transfer functions provided. Note that the resulting jitter transfer functions for all combinations of inputs (8kHz, 1.544MHz, 2.048MHz) and outputs (8kHz, 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz, 19.44MHz) for a given input signal (jitter frequency and jitter amplitude) are the same. Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter signals (e.g., 75% of the specified maximum jitter tolerance). Frequency Accuracy Frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an external reference, but is operating in a free running mode. For the MT9045, the Freerun accuracy is equal to the Master Clock (OSCi) accuracy. Holdover Accuracy Holdover accuracy is defined as the absolute tolerance of an output clock signal, when it is not locked to an external reference signal, but is operating using storage techniques. For the MT9045, the storage value is determined while the device is in Normal Mode and locked to an external reference signal. The absolute Master Clock (OSCi) accuracy of the MT9045 does not affect Holdover accuracy, but the change in OSCi accuracy while in Holdover Mode does.
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Capture Range
Data Sheet
Also referred to as pull-in range. This is the input frequency range over which the synchronizer must be able to pull into synchronization. The MT9045 capture range is equal to 230 ppm minus the accuracy of the master clock (OSCi). For example, a 32 ppm master clock results in a capture range of 198 ppm. The Bellcore GR-1244-CORE standard, recommends that the PLL should be able to reject references that are off the nominal frequency by more than 17 ppm. The MT9045 provides two pins, PRIOOR and SECOOR, to indicate whether the primary and secondary reference are within the 17 ppm of the nominal frequency. Both references are monitored at the same time. PRIOOR and SECOOR are updated every 1.0 to 1.5 second. The PRIOOR and SECOOR pins on the MT9045 indicate whether the Primary and Secondary references are within +/- 17ppm of the PLL center frequency. If the Master Oscillator clock input at the OSCi pin has an accuracy of +/-4.6ppm then the effective out of range limits of the PRIOOR and SECOOR pins will be +/-21.6ppm. If there are no clock transitions at the Primary and Secondary reference inputs when the MT9045 is configured to operate with 8kHz or 19.44MHz, then the PRIOOR and SECOOR pins will provide a 50ns high pulse width occurring once every 1.26 seconds. The duration of the pulse width is dependent on the master clock frequency. If there are no clock transitions at the active reference pin, the MT9045 will automatically go to Holdover Mode and indicate this condition with the Holdover pin. Lock Range This is the input frequency range over which the synchronizer must be able to maintain synchronization. The lock range is equal to the capture range for the MT9045. Phase Slope Phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect to an ideal signal. The given signal is typically the output signal. The ideal signal is of constant frequency and is nominally equal to the value of the final output signal or final input signal. Time Interval Error (TIE) TIE is the time delay between a given timing signal and an ideal timing signal. Maximum Time Interval Error (MTIE) MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a particular observation period. MTIE ( S ) = TIEmax ( t ) - TIEmin ( t )
Phase Continuity Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency. Phase continuity applies to the output of the synchronizer after a signal disturbance due to a reference switch or a mode change. The observation period is usually the time from the disturbance, to just after the synchronizer has settled to a steady state. In the case of the MT9045, the output signal phase continuity is maintained to within 5ns at the instance (over one frame) of all reference switches and all mode changes. The total phase shift, depending on the switch or type of mode change, may accumulate up to 200 ns over many frames. The rate of change of the 200 ns phase shift is limited to a maximum phase slope of approximately 5ns/125us. This meets the AT&T TR62411 maximum phase slope requirement of 7.6ns/125us and Bellcore GR-1244-CORE (81ns/1.326ms).
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Phase Lock Time
Data Sheet
This is the time it takes the synchronizer to phase lock to the input signal. Phase lock occurs when the input signal and output signal are not changing in phase with respect to each other (not including jitter). Lock time is very difficult to determine because it is affected by many factors which include: * * * * initial input to output phase difference initial input to output frequency difference synchronizer loop filter synchronizer limiter
Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements. For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock time. And better (smaller) phase slope performance (limiter) results in longer lock times. The MT9045 loop filter and limiter were optimized to meet the AT&T TR62411 jitter transfer and phase slope requirements. Consequently, phase lock time, which is not a standards requirement, may be longer than in other applications. See AC Electrical Characteristics - Performance for Maximum Phase Lock TIme.
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Description Input Controls MS2 0 0 0 0 0 1 MS1 0 0 0 1 1 0 RSEL 0 0 1 0 1 X PCCi 0 1 X X X X Freerun S0 S1 S1 S2 / / Normal (PRI) S1 S2 MTIE S1H S2H S0 State Normal (SEC) S2 S1 MTIE S1 MTIE / S2H S0 Holdover (PRI) S1H S1 S1 MTIE S2 MTIE / S0
Data Sheet
Holdover (SEC) S2H S1 MTIE S1 MTIE S2 MTIE / S0
Legend: No Change / Not Valid MTIE State change occurs with TIE Corrector Circuit Refer to Control State Diagram for state changes to and from Auto-Holdover State
Table 4 - Control State Table
S0 Freerun (10X)
S1 Normal Primary (000)
{A}
S1A Auto-Holdover Primary (000)
S2A Auto-Holdover Secondary (001)
{A}
S2 Normal Secondary (001)
(PCCi=0) (PCCi=1)
S1H Holdover Primary (010)
S2H Holdover Secondary (011)
NOTES: (XXX) MS2 MS1 RSEL {A} Invalid Reference Signal Movement to Normal State from any state requires a valid input signal
Phase Re-Alignment Phase Continuity Maintained (without TIE Corrector Circuit) Phase Continuity Maintained (with TIE Corrector Circuit)
Figure 7 - Control State Diagram
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Data Sheet
MT9045 provides a fast lock pin (FLOCK), which, when set high enables the PLL to lock to an incoming reference within approximately 500 ms.
MT9045 and Network Specifications
The MT9045 fully meets all applicable PLL requirements (intrinsic jitter/wander, jitter/wander tolerance, jitter/wander transfer, frequency accuracy, frequency holdover accuracy, capture range, phase change slope and MTIE during reference rearrangement) for the following specifications. 1. Bellcore GR-1244-CORE June 1995 for Stratum 3, Stratum 4 Enhanced and Stratum 4 2. AT&T TR62411 (DS1) December 1990 for Stratum 3, Stratum 4 Enhanced and Stratum 4 3. ANSI T1.101 (DS1) February 1994 for Stratum 3, Stratum 4 Enhanced and Stratum 4 4. ETSI 300 011 (E1) April 1992 for Single Access and Multi Access 5. TBR 4 November 1995 6. TBR 12 December 1993 7. TBR 13 January 1996 8. TU-T I.431 March 1993 9. TU-T G.813 August 1996 for Option1 clocks for 2048 kbit/s interfaces 10. ITU-T G.812 June 1998 for type IV clocks for 1,544 kbit/s interfaces and 2,048 kbit/s interfaces
Applications
This section contains MT9045 application specific details for clock and crystal operation, reset operation, power supply decoupling, and control operation. Master Clock The MT9045 can use either a clock or crystal as the master timing source. In Freerun Mode, the frequency tolerance at the clock outputs is identical to the frequency tolerance of the source at the OSCi pin. For applications not requiring an accurate Freerun Mode, tolerance of the master timing source may be 100ppm. For applications requiring an accurate Freerun Mode, such as AT&T TR62411, the tolerance of the master timing source must be no greater than 32ppm. Another consideration in determining the accuracy of the master timing source is the desired capture range. The sum of the accuracy of the master timing source and the capture range of the MT9045 will always equal 230ppm. For example, if the master timing source is 100ppm, then the capture range will be 130ppm. Clock Oscillator - when selecting a Clock Oscillator, numerous parameters must be considered. This includes absolute frequency, frequency change over temperature, output rise and fall times, output levels and duty cycle.
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MT9045 OSCi +3.3V
Data Sheet
+3.3V 20MHz OUT GND
0.1uF
OSCo No Connection
Figure 8 - Clock Oscillator Circuit For applications requiring 32ppm clock accuracy, the following clock oscillator module may be used. FOX F7C-2E3-20.0MHz Frequency: 20MHz Tolerance: 25ppm 0C to 70C Rise & Fall Time:10ns (0.33V 2.97V 15pF) Duty Cycle: 40% to 60% The output clock should be connected directly (not AC coupled) to the OSCi input of the MT9045, and the OSCo output should be left open as shown in Figure 8. Crystal Oscillator - Alternatively, a Crystal Oscillator may be used. A complete oscillator circuit made up of a crystal, resistor and capacitors is shown in Figure 9.
MT9045 OSCi 20MHz 1M
56pF OSCo 100
39pF
3-50pF
1uH
1uH inductor: may improve stability and is optional
Figure 9 - Crystal Oscillator Circuit The accuracy of a crystal oscillator depends on the crystal tolerance as well as the load capacitance tolerance. Typically, for a 20MHz crystal specified with a 32pF load capacitance, each 1pF change in load capacitance contributes approximately 9ppm to the frequency deviation. Consequently, capacitor tolerances, and stray capacitances have a major effect on the accuracy of the oscillator frequency. The trimmer capacitor shown in Figure 9 may be used to compensate for capacitive effects. If accuracy is not a concern, then the trimmer may be removed, the 39pF capacitor may be increased to 56pF, and a wider tolerance crystal may be substituted.
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Data Sheet
The crystal should be a fundamental mode type - not an overtone. The fundamental mode crystal permits a simpler oscillator circuit with no additional filter components and is less likely to generate spurious responses. The crystal specification is as follows. Frequency: Tolerance: Oscillation Mode: Resonance Mode: Load Capacitance: 20MHz As required Fundamental Parallel 32pF
Maximum Series Resistance:35 Approximate Drive Level: e.g., R1B23B32-20.0MHz (20ppm absolute, 6ppm 0C to 50C, 32pF, 25) TIE Correction (using PCCi) When Primary Holdover Mode is entered for short time periods, TIE correction should not be enabled. This will prevent unwanted accumulated phase change between the input and output. For instance, 10 Normal to Holdover to Normal mode change sequences occur, and in each case Holdover was entered for 2s. Each mode change sequence could account for a phase change as large as 350ns. Thus, the accumulated phase change could be as large as 3.5us, and, the overall MTIE could be as large as 3.5us. Phase hold = 0.05ppm x 2s = 100ns Phase state = 50ns + 200ns = 250ns Phase 10 = 10 x ( 250ns + 100ns ) = 3.5us 1mW
* * *
0.05ppm is the accuracy of Holdover Mode 50ns is the maximum phase continuity of the MT9045 from Normal Mode to Holdover Mode 200ns is the maximum phase continuity of the MT9045 from Holdover Mode to Normal Mode (with or without TIE Corrector Circuit)
When 10 Normal to Holdover to Normal mode change sequences occur without MTIE enabled, and in each case holdover was entered for 2s, each mode change sequence could still account for a phase change as large as 350ns. However, there would be no accumulated phase change, since the input to output phase is re-aligned after every Holdover to Normal state change. The overall MTIE would only be 350ns. Reset Circuit A simple power up reset circuit with about a 50us reset low time is shown in Figure 10. Resistor RP is for protection only and limits current into the RST pin during power down conditions. The reset low time is not critical but should be greater than 300ns.
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MT9045 +3.3V R 10k RST RP 1k
Data Sheet
C 10nF
Figure 10 - Power-Up Reset Circuit
Lock Indicator
The LOCK pin toggles at a random rate when the PLL is frequency locked to the input reference. In Figure 11 the RC-time-constant circuit can be used to hold the high state of the LOCK pin. Once the PLL is frequency locked to the input reference, the minimum duration of LOCK pin's high state would be 32ms and the maximum duration of LOCK pin's low state would not exceed 1 second. The following equations can be used to calculate the charge and discharge times of the capacitor.
tC = - RD C ln(1 - VT+ /VDD) = 240 s tC = Capacitor's charge time RD = Dynamic resistance of the diode (100 ) C = Capacitor value (1F) VT+ = Positive going threshold voltage of the Schmitt Trigger (3.0 V) VDD = 3.3 V
tD = - R C ln(VT- /VDD) = 1.65 seconds tD = Capacitor's discharge time R = Resistor value (3.3 M) C = Capacitor value (1F) VT- = Negative going threshold voltage of the Schmitt Trigger (2.0 V) VDD = 3.3 V
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Data Sheet
MT9045 Lock
R=3.3M
74HC14
74HC14 LOCK
IN4148
+
C=1f
Figure 11 - Time-constant Circuit A digital alternative to the RC-time-constant circuit is presented in Figure 12. The circuit in Figure 12 can be used to generate a steady lock signal. The circuit monitors the MT9045's LOCK pin, as long as it detects a positive pulse every 1.024 seconds or less, the Advanced Lock output will remain high. If no positive pulse is detected on the LOCK output within 1.024 seconds, the Advanced LOCK output will go low.
Figure 12 - Digital Lock Pin Circuit
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Absolute Maximum Ratings* - Voltages are with respect to ground (VSS) unless otherwise stated.
Parameter 1 2 3 4 Supply voltage Voltage on any pin Current on any pin Storage temperature Symbol VDD VPIN IPIN TST -55 Min -0.3 -0.3 Max 7.0
Data Sheet
Units V V mA C mW
VDD+ 0.3 30 125
5 48 SSOP package power dissipation PPD 200 * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 2 Supply voltage Operating temperature Sym VDD TA Min 3.0 -40 Max 3.6 85 Units V C
DC Electrical Characteristics* - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 2 3 4 5 6 7 Supply current with: OSCi = 0V OSCi = Clock CMOS high-level input voltage CMOS low-level input voltage Input leakage current High-level output voltage Low-level output voltage Sym IDDS IDD VCIH VCIL IIL VOH VOL -15 2.4 0.4 0.7VDD 0.3VDD 15 Min Max 1.8 50 Units mA mA V V A V V VI=VDD or 0V IOH= 10 mA IOL= 10 mA Conditions/Notes Outputs unloaded Outputs unloaded
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
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AC Electrical Characteristics - Performance
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
See "Notes" following AC Electrical Characteristics tables.
Data Sheet
Sym 0ppm 32ppm 100ppm 0ppm 32ppm 100ppm 0ppm 32ppm 100ppm
Min -0 -32 -100 -0.05 -0.05 -0.05 -230 -198 -130
Max +0 +32 +100 +0.05 +0.05 +0.05 +230 +198 +130 30
Units ppm ppm ppm ppm ppm ppm ppm ppm ppm s ns ns ns ns ns us/s ppm ppm ppm
Conditions/ Notes 5-9 5-9 5-9 1,2,4,6-9,41 1,2,4,6-9,41 1,2,4,6-9,41 1-3,6-9 1-3,6-9 1-3,6-9 1-3,6-15 1-3,6-15 1-2,4-15 1-,4,6-15 1-3,6-15 1-15,28 1-15,28 1-3,6,9,10-12 1-3,7,10-12 1-3,8,10-12
Freerun Mode accuracy with OSCi at:
Holdover Mode accuracy with OSCi at:
Capture range with OSCi at:
Phase lock time Output phase continuity with: reference switch mode switch to Normal mode switch to Freerun mode switch to Holdover MTIE (maximum time interval error) Output phase slope Reference input for Auto-Holdover with: 8kHz, 19.44MHz 1.544MHz 2.048MHz -30k -30k -30k
200 200 200 50 600 45 +30k +30k +30k
AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels* - Voltages are
with respect to ground (VSS) unless otherwise stated
Characteristics 1 2 3 Threshold Voltage Rise and Fall Threshold Voltage High Rise and Fall Threshold Voltage Low
Sym VT VHM VLM
CMOS 0.5VDD 0.7VDD 0.3VDD
Units V V V
* Supply voltage and operating temperature are as per Recommended Operating Conditions. * Timing for input and output signals is based on the worst case result of the CMOS thresholds. * See Figure 12.
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Data Sheet
Timing Reference Points ALL SIGNALS tIRF, tORF tIRF, tORF V HM VT V LM
Figure 13 - Timing Parameter Measurement Voltage Levels
AC Electrical Characteristics - Input/Output Timing
tR8D PRI/SEC 8kHz tR15D PRI/SEC 1.544MHz tR2D PRI/SEC 2.048MHz PRI/SEC 19.44MHz F8o VT NOTES: 1. Input to output delay values are valid after a TCLR or RST with no further state changes tRW VT tRW VT tRW VT tR19D tRW VT
Figure 14 - Input to Output Timing (Normal Mode)
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Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Reference input pulse width high or low Reference input rise or fall time 8kHz reference input to F8o delay 1.544MHz reference input to F8o delay 2.048MHz reference input to F8o delay 19.44MHz reference input to F8o delay F8o to F0o delay F16o setup to C16o falling F16o hold to C16o rising F8o to C1.5o delay F8o to C6o delay F8o to C2o delay F8o to C4o delay F8o to C8o delay F8o to C16o delay F8o to TSP delay F8o to RSP delay F8o to C19o delay C1.5o pulse width high or low C6o pulse width high or low C2o pulse width high or low C4o pulse width high or low C8o pulse width high or low C16o pulse width high or low TSP pulse width high RSP pulse width high C19o pulse width high C19o pulse width low F0o pulse width low F8o pulse width high F16o pulse width low Output clock and frame pulse rise or fall time Input Controls Setup Time Input Controls Hold Time Sym tRW tIRF tR8D tR15D tR2D tR19D tF0D tF16S tF16H tC15D tC6D tC2D tC4D tC8D tC16D tTSPD tRSPD tC19D tC15W tC6W tC2W tC4W tC8W tC16WL tTSPW tRSPW tC19WH tC19WL tF0WL tF8WH tF16WL tORF tS tH 100 100 -21 337 222 46 111 25 -10 -45 -10 -11 -11 -11 -11 -6 -8 -15 309 70 230 111 52 24 478 474 25 17 234 109 47 Min 100 10 6 363 238 57 130 40 10 -25 10 5 5 5 5 10 8 5 339 86 258 133 70 35 494 491 35 25 254 135 75 9 Max
Data Sheet
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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tF8WH F8o tF0WL F0o tF16WL F16o tC16WL C16o tC8W C8o tC4W C4o tC2W C2o tC6W C6o tC6W tC6D tC2D tC4W tC4D tC8W tC8D tF16S tF16H tF16D tF0D
Data Sheet
VT
VT
VT
tC16D
VT
VT
VT
VT
VT
tC15W C1.5o tC19W tC19W C19o
tC15D VT
tC19D
VT
Figure 15 - Output Timing 1
F8o
VT
C2o
VT
tRSPD
RSP tTSPW TSP tTSPD tRSPW VT VT
Figure 16 - Output Timing 2
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Data Sheet
F8o tS tH
VT
MS1,2, RSEL, PCCi Figure 17 - Input Controls Setup and Hold Timing
VT
AC Electrical Characteristics - Intrinsic Jitter Unfiltered
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 Intrinsic jitter at F8o (8kHz) Intrinsic jitter at F0o (8kHz) Intrinsic jitter at F16o (8kHz) Intrinsic jitter at C1.5o (1.544MHz) Intrinsic jitter at C2o (2.048MHz) Intrinsic jitter at C6o (6.312MHz) Intrinsic jitter at C4o (4.096MHz) Intrinsic jitter at C8o (8.192MHz) Intrinsic jitter at C16o (16.384MHz) Intrinsic jitter at TSP (8kHz) Intrinsic jitter at RSP (8kHz) Intrinsic jitter at C19o (19.44MHz) Sym Max 0.0002 0.0002 0.0002 0.030 0.040 0.120 0.080 0.104 0.104 0.0002 0.0002 0.27 Units UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp Conditions/Notes 1-15,22-25,29 1-15,22-25,29 1-15,22-25,29 1-15,22-25,30 1-15,22-25,31 1-15,22-25,32 1-15,22-25,33 1-15,22-25,34 1-15,22-25,35 1-15,22-25,35 1-15,22-25,35 1-15,22-25,36
See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - C1.5o (1.544MHz) Intrinsic Jitter Filtered
Characteristics 1 2 3 4 Intrinsic jitter (4Hz to 100kHz filter) Intrinsic jitter (10Hz to 40kHz filter) Intrinsic jitter (8kHz to 40kHz filter) Intrinsic jitter (10Hz to 8kHz filter) Sym Min Max 0.015 0.010 0.010 0.005 Units UIpp UIpp UIpp UIpp Conditions/Notes 1-15,22-25,30 1-15,22-25,30 1-15,22-25,30 1-15,22-25,30
See "Notes" following AC Electrical Characteristics tables.
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AC Electrical Characteristics - C2o (2.048MHz) Intrinsic Jitter Filtered
Characteristics 1 2 3 4 Intrinsic jitter (4Hz to 100kHz filter) Intrinsic jitter (10Hz to 40kHz filter) Intrinsic jitter (8kHz to 40kHz filter) Intrinsic jitter (10Hz to 8kHz filter) Sym Min Max 0.015 0.010 0.010 0.005 Units UIpp UIpp UIpp UIpp
Data Sheet
Conditions/Notes 1-15,22-25,31 1-15,22-25,31 1-15,22-25,31 1-15,22-25,31
See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - 8kHz Input to 8kHz Output Jitter Transfer
Characteristics 1 2 3 4 5 6 Jitter attenuation for 1Hz@0.01UIpp input Jitter attenuation for 1Hz@0.54UIpp input Jitter attenuation for 10Hz@0.10UIpp input Jitter attenuation for 60Hz@0.10UIpp input Jitter attenuation for 300Hz@0.10UIpp input Jitter attenuation for 3600Hz@0.005UIpp input Sym Min 0 6 12 28 42 45 Max 6 16 22 38 Units dB dB dB dB dB dB Conditions/Notes 1-3, 6, 10 -15, 22-23, 25, 29, 37 1-3,6,10 -15, 22-23, 25, 29, 37 1-3, 6,10 -15, 22-23,25,29,37 1-3,6,10-15, 22-23,25,29,37 1-3,6,10 -15, 22-23,25,29,37 1-3,6,10 -15, 22-23,25,29,37
See "Notes" following AC Electrical Characteristics tables.
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Data Sheet
AC Electrical Characteristics - 1.544MHz Input to 1.544MHz Output Jitter Transfer
Characteristics 1 2 3 4 5 6 7 Jitter attenuation for 1Hz@20UIpp input Jitter attenuation for 1Hz@104UIpp input Jitter attenuation for 10Hz@20UIpp input Jitter attenuation for 60Hz@20UIpp input Jitter attenuation for 300Hz@20UIpp input Jitter attenuation for 10kHz@0.3UIpp input Jitter attenuation for 100kHz@0.3UIpp input Sym Min 0 6 12 28 42 45 45 Max 6 16 22 38 Units dB dB dB dB dB dB dB Conditions/Notes 1-3,7,10 -15, 22-23,25,30,37 1-3,7,10 -15, 22-23,25,30,37 1-3,7,10 -15, 22-23,25,30,37 1-3,7,10 -15, 22-23,25,30,37 1-3,7,10-15, 22-23,25,30,37 1-3,7,10-15, 22-23,25,30,37 1-3,7,10-15, 22-23,25,30,37
See "Notes" following AC Electrical Characteristics tables.
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Data Sheet
AC Electrical Characteristics - 2.048MHz Input to 2.048MHz Output Jitter Transfer
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Jitter at output for 1Hz@3.00UIpp input with 40Hz to 100kHz filter Sym Min Max 2.9 0.09 1.3 0.10 0.80 0.10 0.40 0.10 0.06 0.05 0.04 0.03 0.04 0.02 Units UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp Conditions/Notes 1-3,8,10 -15, 22-23,25,31,37 1-3,8,10 -15, 22-23,25,31,38 1-3,8,10 -15, 22-23,25,31,37 1-3,8,10 -15, 22-23,25,31,38 1-3,8,10-15, 22-23,25,31,37 1-3,8,10-15, 22-23,25,31,38 1-3,8,10-15, 22-23,25,31,37 1-3,8,10-15, 22-23,25,31,38 1-3,8,10-15, 22-23,25,31,37 1-3,8,10-15, 22-23,25,31,38 1-3,8,10-15, 22-23,25,31,37 1-3,8,10-15, 22-23,25,31,38 1-3,8,10-15, 22-23,25,31,37 1-3,8,10-15, 22-23,25,31,36
Jitter at output for 3Hz@2.33UIpp input with 40Hz to 100kHz filter
Jitter at output for 5Hz@2.07UIpp input with 40Hz to 100kHz filter
Jitter at output for 10Hz@1.76UIpp input with 40Hz to 100kHz filter
Jitter at output for 100Hz@1.50UIpp input with 40Hz to 100kHz filter
Jitter at output for 2400Hz@1.50UIpp input with 40Hz to 100kHz filter
Jitter at output for 100kHz@0.20UIpp input with 40Hz to 100kHz filter
See "Notes" following AC Electrical Characteristics tables.
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AC Electrical Characteristics - 8kHz Input Jitter Tolerance
Characteristics 1 2 3 4 5 6 7 8 Jitter tolerance for 1Hz input Jitter tolerance for 5Hz input Jitter tolerance for 20Hz input Jitter tolerance for 300Hz input Jitter tolerance for 400Hz input Jitter tolerance for 700Hz input Jitter tolerance for 2400Hz input Jitter tolerance for 3600Hz input Sym Min 0.80 0.70 0.60 0.20 0.15 0.08 0.02 0.01 Max Units UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp
Data Sheet
Conditions/Notes 1-3,6,10 -15,22-23,25-27,29 1-3,6,10 -15,22-23,25-27,29 1-3,6,10 -15,22-23,25-27,29 1-3,6,10 -15,22-23,25-27,29 1-3,6,10 -15,22-23,25-27,29 1-3,6,10 -15,22-23,25-27,29 1-3,6,10 -15,22-23,25-27,29 1-3,6,10 -15,22-23,25-27,29
See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - 1.544MHz Input Jitter Tolerance
Characteristics 1 2 3 4 5 6 7 8 9 Jitter tolerance for 1Hz input Jitter tolerance for 5Hz input Jitter tolerance for 20Hz input Jitter tolerance for 300Hz input Jitter tolerance for 400Hz input Jitter tolerance for 700Hz input Jitter tolerance for 2400Hz input Jitter tolerance for 10kHz input Jitter tolerance for 100kHz input Sym Min 150 140 130 35 25 15 4 1 0.5 Max Units UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp Conditions/Notes 1-3,7,10 -15,22-23,25-27,30 1-3,7,10 -15,22-23,25-27,30 1-3,7,10 -15,22-23,25-27,30 1-3,7,10 -15,22-23,25-27,30 1-3,7,10 -15,22-23,25-27,30 1-3,7,10 -15,22-23,25-27,30 1-3,7,10 -15,22-23,25-27,30 1-3,7,10 -15,22-23,25-27,30 1-3,7,10 -15,22-23,25-27,30
See "Notes" following AC Electrical Characteristics tables.
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AC Electrical Characteristics - 2.048MHz Input Jitter Tolerance
Characteristics 1 2 3 4 5 6 7 8 9 Jitter tolerance for 1Hz input Jitter tolerance for 5Hz input Jitter tolerance for 20Hz input Jitter tolerance for 300Hz input Jitter tolerance for 400Hz input Jitter tolerance for 700Hz input Jitter tolerance for 2400Hz input Jitter tolerance for 10kHz input Jitter tolerance for 100kHz input Sym Min 150 140 130 50 40 20 5 1 1 Max Units UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp
Data Sheet
Conditions/Notes 1-3,8,10 -15,22-23,25-27,31 1-3,8,10 -15,22-23,25-27,31 1-3,8,10 -15,22-23,25-27,31 1-3,8,10 -15,22-23,25-27,31 1-3,8,10 -15,22-23,25-27,31 1-3,8,10 -15,22-23,25-27,31 1-3,8,10 -15,22-23,25-27,31 1-3,8,10 -15,22-23,25-27,31 1-3,8,10 -15,22-23,25-27,31
See "Notes" following AC Electrical Characteristics tables.
AC Electrical Characteristics - OSCi 20MHz Master Clock Input
Characteristics 1 2 3 4 5 6 Duty cycle Rise time Fall time Tolerance Sym Min -0 -32 -100 40 Max +0 +32 +100 60 10 10 Units ppm ppm ppm % ns ns Conditions/Notes 16,19 17,20 18,21
See "Notes" following AC Electrical Characteristics tables.
Notes:
Voltages are with respect to ground (VSS) unless otherwise stated. Supply voltage and operating temperature are as per Recommended Operating Conditions. Timing parameters are as per AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels 1. PRI reference input selected. 2. SEC reference input selected. 3. Normal Mode selected. 4. Holdover Mode selected. 5. Freerun Mode selected. 6. 8kHz Frequency Mode selected. 7. 1.544MHz Frequency Mode selected. 8. 2.048MHz Frequency Mode selected. 9. 19.44MHz Frequency Mode selected. 10. Master clock input OSCi at 20MHz 0ppm. 11. Master clock input OSCi at 20MHz 32ppm. 12. Master clock input OSCi at 20MHz 100ppm. 13. Selected reference input at 0ppm. 14. Selected reference input at 32ppm. 15. Selected reference input at 100ppm. 16. For Freerun Mode of 0ppm. 17. For Freerun Mode of 32ppm. 18. For Freerun Mode of 100ppm. 19. For capture range of 230ppm. 20. For capture range of 198ppm. 21. For capture range of 130ppm. 22. 25pF capacitive load.
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Zarlink Semiconductor Inc.
MT9045
23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. OSCi Master Clock jitter is less than 2nspp, or 0.04UIpp where1UIpp=1/20MHz. Jitter on reference input is less than 7nspp. Applied jitter is sinusoidal. Minimum applied input jitter magnitude to regain synchronization. Loss of synchronization is obtained at slightly higher input jitter amplitudes. Within 10ms of the state, reference or input change. 1UIpp = 125us for 8kHz signals. 1UIpp = 648ns for 1.544MHz signals. 1UIpp = 488ns for 2.048MHz signals. 1UIpp = 323ns for 3.088MHz signals. 1UIpp = 244ns for 4.096MHz signals. 1UIpp = 122ns for 8.192MHz signals. 1UIpp = 61ns for 16.384MHz signals. 1UIpp = 51.44ns for 19.44MHz signals. No filter. 40Hz to 100kHz bandpass filter. With respect to reference input signal frequency. After a RST or TCLR. Master clock duty cycle 40% to 60%. Prior to Holdover Mode, device was in Normal Mode and phase locked.
Data Sheet
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Zarlink Semiconductor Inc.
c Zarlink Semiconductor 2003 All rights reserved.
Package Code Previous package codes
ISSUE ACN DATE APPRD.
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